![]() For the first step, the input 6.3 V is compared to 8 V (the midpoint of the 0–16 V range). For example, consider an input voltage of 6.3 V and the initial range is 0 to 16 V. At each step in this process, the approximation is stored in a successive approximation register (SAR). At each successive step, the converter compares the input voltage to the output of an internal digital to analog converter which might represent the midpoint of a selected voltage range. A successive-approximation ADC uses a comparator to successively narrow a range that contains the input voltage. ![]() ![]() ![]() They are often used for video, wideband communications or other fast signals in optical storage. Scaling to newer submicrometre technologies does not help as the device mismatch is the dominant design limitation. ADCs of this type have a large die size, a high input capacitance, high power dissipation, and are prone to produce glitches at the output (by outputting an out-of-sequence code). Direct conversion is very fast, capable of gigahertz sampling rates, but usually has only 8 bits of resolution or fewer, since the number of comparators needed, 2N - 1, doubles with each additional bit, requiring a large, expensive circuit. The comparator bank feeds a logic circuit that generates a code for each voltage range. A direct-conversion ADC or flash ADC has a bank of comparators sampling the input signal in parallel, each firing for their decoded voltage range.These are the most common ways of implementing an electronic ADC:
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